1. Field of the Invention
The present invention is directed to testing and screening of integrated circuit dies to detect defective devices. More specifically, but without limitation thereto, the present invention is directed to a method of screening defective dies to achieve maximum stuck-at fault and transition delay fault test coverage for an integrated circuit design.
2. Description of Related Art
Scan based methods for stuck-at fault (SAF) and transition delay fault (TDF) testing of integrated circuit dies generally requires a large number of test patterns to achieve satisfactory test coverage, in some cases, more than 30,000 patterns. Previous methods to reduce the pattern count include inserting logic into the integrated circuit design to perform data compaction, however, this method requires extra resources and added cost. Another method is launch-off shift TDF pattern generation, in which the test pattern transitions are launched during shift. The launch-off shift method has been proven to reduce the number of TDF patterns with higher fault coverage, however, the launch-off shift method requires routing the global scan enable as a clock having a well-controlled insertion delay relationship with all other clocks in the integrated circuit design, which may not be practical in some integrated circuit designs.